LibreLane Configuration Tools

Unified process configuration format supporting both ChipFlow Backend and LibreLane flows.

Overview

This project provides:

• Unified TOML configuration format for process/PDK specifications
• Bidirectional conversion between ChipFlow JSON and unified TOML
• LibreLane variable extraction from unified configs
• Support for both Open and proprietary PDKs

Quick Start

# Install with uv
uv pip install -e .

# Convert ChipFlow JSON to unified TOML
uv run tools/convert_config.py json2toml \
    chipflow.json output.toml \
    --process sky130 --variant hd

# Convert TOML back to ChipFlow JSON
uv run tools/convert_config.py toml2json \
    config.toml output.json

# Test round-trip conversion
uv run tools/convert_config.py test-cfg chipflow.json \
    --process sky130 --variant hd

Documentation

• Configuration Format Specification
• Before/After Enhancement Comparison
• Unified Config Enhancement Details
• ChipFlow vs LibreLane Comparison
• GF130 PDK Structure Analysis

Proposals

• LibreLane Hybrid Configuration System
• Executive Summary

Conversion Tools

Core Converter

tools/convert_config.py - Main conversion tool with four commands:

1. json2toml - Convert ChipFlow JSON to unified TOML
2. toml2json - Convert unified TOML to ChipFlow JSON
3. test - Test JSON → TOML → JSON round-trip
4. test-cfg - Test with CfgFolder validation

Utility Scripts

• regenerate_all_configs.sh - Regenerate all example configs
• verify_librelane_defaults.py - Verify LibreLane compatibility

Example Configs

See configs/processes/ for examples:

• sky130_hd_generated.toml - Sky130 HD with LibreLane defaults
• ihp_sg13g2_generated.toml - IHP SG13G2
• gf130_bcd_generated.toml - GF130 BCD (proprietary)
• helvellyn2_base_generated.toml - Helvellyn2

Features

Unified Format v2.0

Single TOML format supporting both systems:

[meta]
format_version = "2.0"
process = "sky130"
variant = "hd"
target_systems = ["chipflow", "librelane"]

[pdk]
name = "sky130A"
std_cell_library = "sky130_fd_sc_hd"

[pdk.power]
vdd_pin = "VPWR"
vdd_voltage = "1.80"
gnd_pin = "VGND"

[pdk.std]
liberty = { "nom_*" = ["${std_dir}/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"] }
lef = ["${std_dir}/lef/sky130_fd_sc_hd_merged.lef"]

[pdk.routing]
min_layer = "met1"
max_layer = "met5"

LibreLane Compatibility

Automatic injection of LibreLane-required fields:

• PDK metadata (name, std_cell_library)
• Power/ground configuration (vdd_pin, gnd_pin, power_pins)
• Timing constraints (max_transition)
• Cell definitions (buffer, tap, endcap)

PDK Support

Full support (11/11 LibreLane fields):

• Sky130 (Open PDK)
• IHP SG13G2 (Open PDK)
• GF130 BCD (Proprietary)
• GF180MCU (Open PDK)

Partial support:

• Helvellyn2 (9/11 fields)

Development

# Run tests
pytest

# Verify all configs
uv run verify_librelane_defaults.py

# Regenerate all example configs
./regenerate_all_configs.sh

License

See LICENSE file.

Contributing

Contributions welcome! Please see CONTRIBUTING.md for guidelines.