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  1. rv32i-tlv-cpu rv32i-tlv-cpu Public

    Fully functional 32-bit RV32I RISC-V single-cycle CPU core implemented in TL-Verilog using Makerchip

    M4 2

  2. lock_project lock_project Public

    A 3-digit Electronic Code Lock digital design implemented in Verilog using a Finite State Machine (FSM).

    Verilog

  3. riscv-5stage-core riscv-5stage-core Public

    Verilog