Fix Verilog top module detection for modules with a parameter block

[Copilot]

A Verilog module declared with a parameter block (#( ... )) before its port list was not recognized as a top module. VerilogNodeProvider.ParseModules consumed the balanced parameter block but did not skip whitespace before expecting the port-list (, so any newline/space between ) and ( caused the module to be misclassified as portless and dropped.

module my_custom_top #(
    parameter DATA_WIDTH = 32
)
(                        // <- whitespace/newline here caused the module to be skipped
    input wire clk,
    output reg data_out
);
endmodule

Changes

• Parser fix (src/OneWare.Verilog/Parsing/VerilogNodeProvider.cs): skip whitespace after the #( ... ) parameter block before matching the port-list (.
• Testability refactor: extracted internal static string-based helpers (ExtractNodes, ExtractTopEntities) so parsing can be tested on raw source without constructing an IProjectFile. The public file-based API is unchanged.
• Tests: new tests/OneWare.Verilog.UnitTests project (added to OneWare.slnx, wired via InternalsVisibleTo) covering parameterized modules with and without whitespace before the port list, plain modules, and port extraction.