Stochastic Computing for Deep Neural Networks

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Generating Posit-Based Accelerators With High-Level Synthesis

Code for reproducing CoNGA 2022 results on posit arithmetic operators

A 32 bit Booth Encoded Wallace Tree Multiplier in Verilog HDL.

Assignment codes for Introduction to Numerical Analysis (2020, FGV-EMAp).

POPiX: Floating to Fixed-Point Code Generator

Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.

Code for reproducing CoNGA 2023 results on approximate posit arithmetic

Design and implementation of RISC-V processor with a single-cycle datapath and controller.

Design and implementation of RISC-V processor with a multi-cycle datapath and controller.

Учебный C++ проект по машинной арифметике: перевод чисел между системами счисления, формат IEEE-754 и побитовая реализация сложения, вычитания, умножения и деления для целых и дробных чисел.

Naive x86_64 assembly for big integer arithmetics and generating binary factorial tables

Study of Montgomery Modular Multiplication in Residue Number Systems

Course Taken @ UCMerced [2021]

Simulations of the following computer arithmetic algorithms: Booth, Booth Radix4, Restoring, Non-Restoring, Radix4 SRT, Radix2 SRT